1. Field of the Invention
The invention relates to the field of electronic circuits, and in particular, to an accurate full speed/low speed mode driver for a USB 2.0 transceiver.
2. Related Art
The Universal Serial Bus (USB) protocol is a popular communications protocol that enables communications between a wide range of modern electronic devices and computer peripherals (e.g., scanners, digital cameras, personal digital assistants, and digital music players). The present USB 2.0 specification (“Universal Serial Bus Specification”, Revision 2.0, Apr. 27, 2000) defines three signaling levels that can be supported by USB-compliant devices. The three levels include a low-speed (LS) mode operating at 1.5 Mbps at 3.3 V, a full-speed (FS) mode operating at 12 Mbps at 3.3 V, and a high-speed (HS) mode that signals at 480 Mbps at 400 mV.
The USB 2.0 specification imposes rigid performance requirements on the legacy modes of operation (i.e., the LS and FS modes) to ensure compatibility with older FS/LS-only devices. Those performance requirements include specific rise/fall time durations and crossing voltages. For example, a legacy LS rise/fall time must be within the range of 75 to 300 ns, while a legacy FS rise/fall time must be within the range of 8 to 20 ns. In both legacy LS and FS modes, crossing voltage (i.e., the voltage at which the transitioning differential USB signals DP and DM intersect) must be between 1.3 V and 2.0 V.
Unfortunately, the high speeds at which modern semiconductor devices and circuits typically run can make it difficult to control the relatively long duration legacy FS and LS transitions. Not only must the rise and fall times be throttled down to relatively slow rates, but individual rise and fall times must be well controlled to ensure proper crossing voltage performance. In an effort to reduce output rise times, conventional FS/LS mode drivers in USB 2.0 transceivers generally include a large capacitor to reduce the output slew rates. For example, FIG. 1A shows a conventional legacy FS/LS USB driver 100A that includes a PMOS transistor P110, an NMOS transistor N120, an output resistor R130, and an output capacitor C140. PMOS transistor P110 and NMOS transistor N120 are connected in series between an upper supply voltage VDD and ground to form an inverter. Resistor R130 is connected between the junction of transistors P110 and N120 (i.e., the inverter output) and an output terminal 102, while output capacitor C140 is connected between output terminal 102 and ground.
When FS or LS USB data DATA_N is provided to an input terminal 101 at the gates of transistors P110 and N120 (i.e., at the inverter input), the signal is inverted and fed out to output terminal 102 through output resistor R130 to generate a USB output signal DP (in a substantially similar manner, a complementary driver (not shown) would produce complementary signal DM in response to complementary USB data DATA to form the other half of the complete differential USB signal). The presence of output capacitor C140 is intended to reduce the slew rate of output signal DP so that the FS/LS signal requirements of the USB 2.0 Specification can be met. Specifically, output capacitor C140 is sized to provide an RC time constant (in conjunction with output resistor R130) that limits the slew rate of output signal DP to an acceptable level (the size of output resistor R130 is defined by the USB 2.0 specification to be 45 ohms).
Unfortunately, output capacitor C140 presents a less-than-ideal solution to the problem of overly rapid rise/fall times and out of bounds crossing voltages. Specifically, the large capacitor required to provide sufficient output slew reduction undesirably increases the size and cost of USB 2.0 transceivers incorporating legacy FS/LS USB driver 100A. In addition, accurate control over the capacitance of output capacitor C140 can be difficult to achieve using conventional semiconductor manufacturing processes, which in turn can reduce the yield for USB 2.0 transceivers incorporating legacy FS/LS USB driver 100A.
To overcome some of the limitations associated with legacy FS/LS USB driver 100A, a Miller capacitor can be used in place of output capacitor C140. For example, FIG. 1B shows a legacy FS/LS USB driver 100B that is substantially similar to driver 100A shown in FIG. 1A, except that output capacitor C140 is replaced with a Miller capacitor C150. Miller capacitor C150 is connected between input terminal 101 and output terminal 102 of legacy FS/LS USB driver 100B. Due to this bridging of input terminal 101 and output terminal 102, Miller capacitor C150 exhibits the well-known “Miller Effect” that multiplies its effective capacitance as seen by output terminal 102. Therefore, the size requirements for Miller capacitor C150 can be reduced over those of output capacitor C140 shown in FIG. 1A, thereby allowing legacy FS/LS USB driver 100B to occupy less die area than legacy FS/LS USB driver 100A.
However, the use of Miller capacitor C150 still involves the use of a relatively space-inefficient capacitor (typically on the order of 140 μm×140 μm), and Miller capacitor C150 exhibits the same problematic capacitance variations associated with output capacitor C140 in FIG. 1A. Furthermore, the CMOS inverter used in conventional legacy FS/LS USB drivers (i.e., the inverter formed by transistors P110 and N120 in drivers 100A and 100B) can make accurate crossing voltage control difficult to achieve, even if the output or Miller capacitor provides sufficient output slew reduction. In particular, the pull-up strength of PMOS transistor P110 and the pull-down strength of NMOS transistor N120 can vary independently with process variations. For example, the pull-up strength and pull-down strength may exhibit a negative correlation (i.e., as the pull-up strength of PMOS transistor P110 increase, the pull-down strength of NMOS transistor N120 will decrease). Therefore, normal process variations will often result in inverters that slew much more rapidly in one direction, which in turn results in crossing voltages that are more likely to fall outside the specified 1.3 V to 2.0 V range.
Accordingly, it is desirable to provide a space-efficient and accurate legacy FS/LS USB driver for a USB 2.0 transceiver.